The shared bench baseline
60 Hz / 325 Vrms / LC choke / 50 mA — the reference every calc uses.
Every measurement in this studio is taken on the same bench. If your numbers don't match, it's either your design (the interesting case) or your bench (the boring case). Knowing the reference makes the difference visible.
- Mains: 60 Hz / 117 Vrms nominal, ±10 % tolerance window.
- Transformer: 325 Vrms secondary each side of CT.
- Rectifier: silicon bridge with ~10 V drop (a tube-rectifier variant is also benched).
- Filter: CLC cap-input (π) — 40 µF / 10 H / 40 µF, choke DCR 100 Ω.
- Load: 50 mA nominal, swept 10 → 100 mA for load-reg tests.
That yields Vraw ≈ 440 V at the reservoir cap (cap-input, near Vpeak) with roughly 800 mV of 120 Hz ripple on that rail — the reference figure every regulator in the course must attenuate. Every topology is measured against this same upstream — same input, comparable output.
1. The instantaneous AC waveform peaks at , related to its rms value by:
2. After the four diodes, every half-cycle is rectified. The unfiltered DC average is the mean of |sin(ωt)| over a full period:
3. Two diodes conduct in series per alternation, so the rectifier subtracts twice the single-diode forward drop:
4. Net unfiltered DC out of the bridge:
5. Both alternations are folded onto the positive rail, so the ripple frequency is twice the mains frequency:
The bench runs a cap-input CLC: the reservoir cap charges to near Vpeak, so Vraw ≈ 440 V — higher, but with more ripple and harder transformer current pulses. The alternative, choke-input (the inductor first, ahead of any cap), would give a stiffer, flatter 0.9 × Vrms,sec ≈ 280 V but needs Iload ≥ a critical current Icrit — better for high-current power amps. The diagram below shows that choke-input variant.
1. In true choke-input mode the choke sees the full half-rectified waveform, so the DC output equals the rectifier’s average:
where V_drops covers bridge diodes plus the choke DCR · I_load.
2. Choke-input mode only holds while load current exceeds the critical current — below it, the filter slumps to cap-input and V_dc climbs toward V_peak. The classic rule of thumb (60 Hz mains):
Equivalent form: I_crit [A] ≈ V_rms / (1000 · L). Keep I_load ≥ ~1.5 · I_crit for margin.
3. Ripple at the input of the LC (≈ half-rectified sine, fundamental at f_ripple) is attenuated by a second-order low-pass. The pk-pk transfer for the dominant harmonic is:
The factor 12 absorbs the Fourier coefficient of the |sin| waveform plus a √2 rms→pk conversion.
1. C1 charges to the AC peak through the rectifier on each half-cycle, then discharges roughly linearly into the load between peaks. The DC sits half a ripple below the peak:
2. Triangle-decay approximation: the reservoir loses charge Q = I_load / f_ripple per cycle, producing a pk-pk ripple on C1 of:
3. The series R and C2 form a single-pole RC low-pass. The pk-pk attenuation at f_ripple is:
R also drops a DC component: V_drop,R = I_load · R — and dissipates I²·R as heat.
4. Final DC at the load:
EU builders: a 50 Hz / 230 V variant of the bench exists. The ripple frequency drops from 120 to 100 Hz, which raises ripple for the same LC. Adjust by larger C2 or a longer choke if the target spec is the same.